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Fault tolerance to support mission life reliability is a key consideration in many system applications. Redundancy for defect tolerance, i.e., yield enhancement, and wafer-level reliability enhancement have been standard practice since the advent of wafer scale technology. Koren [1],[2],[3],[4],[5] and others have shown how effective static redundancy techniques can be for improving both yield and reliability. However, designers are often faced with the conflicting goals of maximizing system reliability and minimizing hardware. Not only are those two goals contradictory, but there is a point of diminishing return relative to the cost effectiveness of increasing system reliability at the expense of adding spare hardware. At ICWSI ‘93, Samson [6] presented an approach for optimizing real-time fault tolerance design in WSI via the Reliability-Availability Product. The approach was based upon the identification of fundamental optimization metrics, represented by simple product and quotient (reciprocal product) relationships, which extend traditional cost/benefit analysis to fault tolerance in VLSI and wafer scale architectures and systems [7]. The Reliability-Hardware Quotient (RHQ) is an example of another fundamental composite metric which is useful for identifying the optimal design point in a VSLI or wafer scale system. In this paper, this metric is applied to the problem of optimizing a two-level distributed (parallel) processing architecture. In particular, a graphical optimization technique using the 3D and contour plot features of Mathematica [8] is introduced which characterizes the trade space and identifies the optimum design point. The constraints of wafer scale technology can be superimposed upon the optimal solution space either to identify the limits of a given wafer scale implementation or to show what level of wafer scale technology is needed to achieve the optimum design.
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