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A Method of Formal Verification of Cryptographic Circuits

Kanji Hirabayashi
Organization: Toshiba Techno Center, Inc., Tokyo, Japan
Journal / Anthology

Journal of Electronic Testing
Year: 1998
Volume: 13
Page range: 321-322

In this letter we report the formal verification of encryption and decryption circuits. After we describe algebraically a simple modular arithmetic circuit at both function and logic levels, we apply the symbolic manipulation of Mathematica.

*Applied Mathematics > Computer Science