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Performance Analysis of an ATM Clos switch under symmetric "bursty geometric" process traffic
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| WESCON/94 Idea/Microelectronics. Conference Record |
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ATM is the new technique recommended by the CCITT for broadband ISDN. Performance of ATM networks will depend on switch performance and architectures. Performance of an ATM switch based on a three-stage Clos interconnection network with non-symmetric switching elements and output buffers is studied under uniform "bursty geometric" arrivals. The output traffic is approximated by a "bursty geometric" process. The model of the switching element is solved for all stages. The output traffic in the previous stage is considered as the input traffic of the next stage. Mathematica 2.1 is used to solve the analytical model of the interconnection network. Discrete event simulations are used to validate our model. Analysis of the results shows the importance of the switch dimensioning.
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