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Title

Thermal Analysis of a Substrate with Power Dissipation in the Vias
Authors

R. Brewster
R. Sherif
Journal / Anthology

IEEE Transactions on Components, Hybrids, and Manufacturing Technology
Year: 1992
Volume: 15
Issue: 5
Page range: 667-674
Description

As power dissipation at the chip level increases, current levels through power distribution wires increase correspondingly. This current flow results in Joule heating in the package, which must be included in any sizing of the package cooling requirements. In this paper, we present an analysis of the temperature field resulting from the Joule heating in a metal wire surrounded by nonheat generating (electrically insulating) material. Exact analytical solutions are given for when the heat generation rate is constant (independent of temperature) and linearly dependent on the temperature. Asymptotic solutions are given for arbitrarily temperature-dependent heat generation, when the insulating material thermal conductivity is much less than the thermal conductivity of the wire. A numerical example of practical interest is then considered. It is shown that neglecting the Joule heating in the wires can result in significant underprediction of the temperature. The effect of temperature on the electrical resistivity of the wire is shown to be negligible. The phenomenon of thermal runaway is also examined using stability theory and is shown to be unimportant in practical circumstances.
Subjects

*Engineering > Electrical Engineering
*Science > Physics > Thermodynamics and Statistical Mechanics